The present invention generally relates to a semiconductor device having an embedded memory and more particularly, to a semiconductor device having an embedded dynamic random access memory.
A dynamic random access memory (DRAM) array is made up of a multitude of one transistor memory cells interconnected into a matrix formation. Interconnecting the memory cells of the DRAM array are multiple bit lines (xe2x80x9ccolumn linesxe2x80x9d) and multiple word lines (xe2x80x9crow linesxe2x80x9d). In the simplest form, each memory cell typically includes of an N channel metal oxide semiconductor transistor, known as an access transistor, and a storage capacitor. The gate of the access transistor is connected to a particular word line, the drain of the access transistor is connected to a bit line and the storage capacitor to the source of the access transistor. Data is stored in the memory cell as a charge on the storage capacitor. Hence, a logically high value (i.e. xe2x80x9c1xe2x80x9d) is stored by charging the capacitor to a high voltage level and a logically low value (i.e. xe2x80x9c0xe2x80x9d) is stored by discharging the capacitor to a low voltage level. Typically all bit lines are precharged to a mid point voltage level approximately equal to one half of a high voltage level (Vdd) and all word lines are precharged to a low voltage level.
The DRAM array is coupled to a word line decoder that selects a particular word line in response to a received word address. The word line decoder selects the decoded word line by raising the voltage of the particular word line to cause all the transistors on the selected word line to become conductive. As a result, the storage capacitors of all the memory cells on the selected word row are coupled to their respective bit lines.
If the memory cell on the selected word row is storing a logic xe2x80x9c0xe2x80x9d, the storage capacitor of the memory cell initially holds a charge of zero volts. Shorting the storage capacitor to the memory cell""s bit line, which capacitance is typically ten to twelve times greater than the capacitance of the storage capacitor, causes the cell storage capacitor to charge and the bit line capacitance to slightly discharge. As a result, the voltage of the corresponding bit line decreases and the voltage decrease is detected by a sense amplifier to which the bit line is coupled. The sense amplifier, in turn, amplifies the detected voltage drop and produces a logic xe2x80x9c0xe2x80x9d value. The amplifier asserts the resulting low voltage value on the bit line to discharge the storage capacity of the selected memory cell back to a logic xe2x80x9c0xe2x80x9d value or zero volts. In this manner, the selected memory cell is restored to its original logic value.
By contrast, if the selected memory cell is storing a logic xe2x80x9c1xe2x80x9d value when its storage capacitor is coupled to the memory cell bit line, the voltage level of the storage capacitor, which is normally lower than the voltage on the bit line, increases slightly. Thus, the discharging of the storage capacitor causes a slight increase in the voltage of the corresponding bit line. The small voltage change in the corresponding bit line is interpreted by the sense amplifier as a logic xe2x80x9c1xe2x80x9d value, and the sense amplifier produces a logic xe2x80x9c1xe2x80x9d voltage value. In turn, the sense amplifier asserts the logic xe2x80x9c1xe2x80x9d voltage value onto the corresponding bit line to charge the storage capacitor back to its original value.
Typically, the storage capacitor of the selected memory cell along with the bit lines of a DRAM device resist any abrupt change in voltage due to their large capacitance value. Consequently, the voltage level of a bit line changes over a period of time. Unfortunately, the input of the sense amplifier is typically cross coupled between two adjacent bit lines, and, as a result, upon completion of a sense operation voltage drop in the input voltage that the amplifier is amplifying. Consequently, the conventional DRAM sense amplifier is burdened with amplifying a variable input signal caused by the charge sharing effect of the selected memory cell and the bit line. As a consequence, the time required to restore a memory cell after a read or write operation occurs is significantly impacted.
The present invention addresses the above-described limitations of conventional sense amplifiers used in a DRAM. The present invention provides an approach to efficiently restore a memory cell of a dynamic random access memory array in less time than a conventional sense amplifier.
In one embodiment of the present invention, a dynamic sense amplifier is provided for a DRAM that reduces the time needed to restore a memory cell after a read operation. The dynamic sense amplifier includes a first inverter cross-coupled with a second inverter. To isolate each of the inverters from their corresponding bit line, the dynamic sense amplifier includes a first switch coupled between the input of the first inverter and the first bit line and a second switch coupled between the input of the second inverter and the second bit line. Each switch of the dynamic sense amplifier is coupled to a control signal to control when each switch is open and closed.
The above described approach benefits a semiconductor device having a DRAM array because the bit line inputs to the dynamic sense amplifier can be isolated from the charge sharing capacitive effects of the bit lines themselves. As a result, when the dynamic sense amplifier attempts to restore a memory cell to its original value following a read or write operation, the input to the amplifier is isolated to expedite restoration. Hence, the input to the dynamic sense amplifier is isolated from the charge sharing effects of the selected memory cell and the corresponding bit line.
In accordance with another aspect of the present invention, a DRAM device is provided with a first bit line and a second bit line coupled to a sense amplifier. The sense amplifier of the DRAM device is coupled to the first bit line and the second bit line through a first switch and a second switch respectively. In this manner, the inputs of the sense amplifier can be isolated from the first bit line and the second bit line when it is necessary to restore or refresh a memory cell of the DRAM.
The above described approach benefits any DRAM architecture that utilizes a DRAM in that the amount of time required to restore a memory cell following a read operation is significantly reduced for example, by ten percent. As a result, microprocessor processing efficiency is increased due to the great reduction in cell restoration time and in similar fashion the efficiency of performing a memory array refresh operation is also increased.
In accordance with still another aspect of the present invention, a method is performed in a DRAM array for restoring a memory cell. When an amplifier of the DRAM array detects a voltage change in a bit line, the amplifier amplifies the voltage change to assert the corresponding logic value. Once the amplifier asserts the logic value corresponding to the detected voltage change, the amplifier""s input is isolated from the bit line to restore the just read memory cell to its original state. The amplifier""s input is isolated from the bit line through the use of a switch. Moreover, the amplifier may service two or more columns of the dynamic random access memory, thus increasing layout efficiency of memory device.